1. Field of the Invention
The invention relates to a semiconductor device, in particular, a semiconductor device including a power MOS transistor with low on-resistance and high switching performance.
2. Description of the Related Art
A power MOS transistor has higher switching performance and more stable performance than a bipolar type power transistor, and thus it is widely used in an inverter circuit for a switching power supply such as a DC-DC converter, an inverter circuit for a motor, and so on.
In recent years, a power MOS transistor used in such circuits needs to have still lower on-resistance and higher switching performance so as to correspond to portable devices becoming smaller and lighter such as a mobile phone. The on-resistance of a power MOS transistor is decreased by increasing the impurity concentration of the drift layer which is a low concentration drain layer.
However, the increasing of the impurity concentration of the drift layer decreases the drain-source breakdown voltage BVDS. In other words, the on-resistance and BVDS are in a tradeoff relation. Therefore, the impurity concentration of the drift layer can not be increased without limit. In order to decrease the on-resistance under a predetermined BVDS, the cross section of the flow path of a drain current need be increased. In other words, the gate width W need be increased.
In this case, finger form electrodes are employed for a drain electrode and a source electrode in order to avoid increasing the die size, in which the drain electrode and the source electrode respectively form a plurality of fingers and these fingers are inserted therebetween. A gate electrode is disposed between the finger form drain electrode and source electrode, and extends from one end to another end of the finger form electrodes.
The switching performance of a power MOS transistor is evaluated using the response speed of the gate voltage VG when a predetermined amount of pulse voltage VP is applied to the gate input terminal. The amount of the gate voltage VG directly applied to the gate electrode right above the channel does not immediately increase and reach the predetermined input pulse voltage VP, and instead increases late after a time depending on the amounts of the gate resistance RG and the gate input capacitance CI.
This delay time is called a rise time trise, and a relation of trise∝RGCI is established. The delay time trise is obtained by subtracting a time taken to reach 0.1 VP from a time taken to reach 0.9 VP when the gate voltage VG to finally reach is VP. The larger the gate resistance RG and the gate input capacitance CI are, the longer the rise time trise of the gate voltage VG is, degrading the switching performance of the power MOS transistor.
Although details will be described below, FIG. 3C shows a rise state of the gate voltage VG of a power MOS transistor 50 shown in FIG. 3A when a pulse voltage VP is applied to the input voltage thereof. The pulse voltage VP is applied to a CR circuit shown in FIG. 3B which is an equivalent circuit of the power MOS transistor 50 in FIG. 3A.
The gate voltage VG rises late after a rise time trise which depends on a time constant RGCI which is the product of the gate resistance RG and the gate input capacitance CI. Furthermore, the gate voltage VG falls late when the pulse voltage VP is turned off, too. Corresponding to the gate voltage VG, fall and rise delay occurs in the drain voltage VD, too, as shown in FIG. 3D. Therefore, when the resistance RG of the gate wiring is large, the switching performance of the power MOS transistor is degraded.
A gate electrode was formerly made of a polysilicon film doped with impurity, but in recent years it was made by layering a metal silicide film on a polysilicon film so as to decrease the gate resistance RG.
Japanese Patent Application Publication No. 2010-171433 discloses decreasing the gate input capacitance CI and gate resistance RG. As to decreasing the gate input capacitance CI, in a power MOS transistor, the gate-drain capacitance CGD which forms the gate input capacitance CI is decreased while an increase of the on-resistance is minimized.
In detail, the gate-drain capacitance CGD is decreased by decreasing the impurity concentration of the drift layer near the channel region so as to make the depletion layer easily extend, thereby decreasing the gate input capacitance CI. On the other hand, the impurity concentration of the drift layer near the drain layer is increased, thereby decreasing the on-resistance.
As to decreasing the gate resistance RG, it is disclosed that a groove is formed in the interlayer insulation film over the gate electrode extending between the drain and the source and a plug electrode is formed by filling the groove with tungsten (W) and used as a gate electrode shunt wiring. Since the metal tungsten (W) is formed to have the same thickness as that of the interlayer insulation film, the gate resistance RG is decreased.
As described in Japanese Patent Application publication No. 2010-171433, by forming the groove in the interlayer insulation film along on the gate electrode extending between the drain and the source and forming the plug electrode filling the groove with tungsten (W) as the gate electrode shunt wiring, the gate resistance RG is decreased to an enough value.
However, in order to satisfy a demand for further enhancing the switching performance, it is necessary to decrease the resistance of the plug electrode made of a tungsten (W) layer. To this end, it is necessary to further increase the thickness and width of the plug electrode made of tungsten (W). However, such a plug electrode with larger thickness and width causes a limit in miniaturizing a wiring pattern.
Therefore, a new means is necessary so as to further decrease the gate resistance RG.